본문 바로가기

Jae-Yoon Sim

소속기관
POSTECH
소속부서
-
직급
-
ORCID
-
연구경력
-

주요 연구분야

  • 공학 > 전자/정보통신공학

저자의 논문 현황

연도별 상세보기를 클릭하시면 연도별 이용수·피인용수 상세 현황을 확인하실 수 있습니다.
피인용수는 저자의 논문이 DBpia 내 인용된 횟수이며, 실제 인용된 횟수보다 적을 수 있습니다.
  • 논문수24
  • 발행기간1993 ~ 2016
  • 이용수615
  • 피인용수1

논문제목를 인용한 논문목록입니다.

  • 피인용 논문 제목
    • 피인용 논문 저자
게시판 목록
논문명 저널명 발행연도 이용수 피인용수
All-Synthesizable 5-Phase Phase-Locked Loop for USB2.0 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2016 6 0
EMI Issues in Pseudo-Differential Signaling for SDRAM Interface JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2015 18 0
An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2015 24 0
A 35 dB-Linear Variable Gain Amplifier Circuit of Digital-Beamformer for Ultrasound Medical Imaging ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2015 17 0
A Delay Locked Loop with an Embedded Duty Cycle Corrector ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2015 14 0
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2015 14 0
A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical Imaging JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2014 41 0
Verilog Synthesis of USB 2.0 Full-speed Device PHY IP 대한전자공학회 ISOCC 2013 15 0
A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver Design JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2013 36 0
A Low-Voltage High-Speed CMOS Inverter-Based Digital Differential Transmitter with Impedance Matching Control and Mismatch Calibration JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2009 42 0
A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2008 66 0
A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization 대한전자공학회 ISOCC 2008 20 0
A 1V 2.8Gbps 0.18μm CMOS Inverter-Based Digital Differential Transmitter with Calibrations of Termination and Mismatch 대한전자공학회 ISOCC 2008 19 0
A SSN-Reduced 5Gb/s Parallel Transmitter JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2007 9 0
A Serpentine Guard Trace to Reduce the Far-end Crosstalk Induced Jitter of Parallel Microstrip Lines 대한전자공학회 ISOCC 2007 9 0
A 5Gb/s 16-bit Transmitter with Segmented Group-Inversion Encoding 대한전자공학회 ISOCC 2007 8 0
A 3Gbps 16-bit Transmitter with Segmented Group-Inversion Encoding 대한전자공학회 ISOCC 2007 2 0
Circuit Design of DRAM for Mobile Generation JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2007 57 1
A Design Guide of 3-stage CMOS Operational Amplifier with Nested Gm-C Frequency Compensation JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2007 36 0
A 0.12㎓-1.4㎓ DLL-based Clock Generator with a Multiplied 4-phase Clock Using a 0.18㎛ CMOS Process JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2006 44 0
더보기