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Seong Mo Park

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한국전자통신연구원
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주요 연구분야

  • 공학 > 전자/정보통신공학

저자의 논문 현황

연도별 상세보기를 클릭하시면 연도별 이용수·피인용수 상세 현황을 확인하실 수 있습니다.
피인용수는 저자의 논문이 DBpia 내 인용된 횟수이며, 실제 인용된 횟수보다 적을 수 있습니다.
  • 논문수24
  • 발행기간1994 ~ 2011
  • 이용수293
  • 피인용수0

논문제목를 인용한 논문목록입니다.

  • 피인용 논문 제목
    • 피인용 논문 저자
게시판 목록
논문명 저널명 발행연도 이용수 피인용수
A 166.7 Mhz 1920x1080 60fps H.264/SVC Video Decoder 대한전자공학회 ISOCC 2011 25 0
Pipeline Power Reduction through Single Comparator-based Clock Gating 대한전자공학회 ISOCC 2009 17 0
Novel RT Level Methodology for Low Power by Using Wasting Toggle Rate based Clock Gating 대한전자공학회 ISOCC 2009 11 0
A 512 Cycles/MB, Enhanced Fast Motion Estimation Strategy for 1080p High Profile H.264/AVC ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2009 26 0
Implementation of 3D Graphics Accelerator using Full Pipeline Scheme on FPGA 대한전자공학회 ISOCC 2008 27 0
Design of Application Specific Processor for H.264 Inverse Transform and Quantization 대한전자공학회 ISOCC 2008 21 0
Efficient Variable Length Decoding Using N-Bit Code Table for Multi-format Video Applications 대한전자공학회 ISOCC 2008 9 0
Design of Application Specific Processor and Compiler forH.264CAVLCDecoding ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2008 11 0
VLSI Implementation of Multilevel Lifting based Discrete Wavelet Transform for JPEG2000 대한전자공학회 ISOCC 2005 2 0
An Implemented of H.264 Video Decoder Based on AMBA Platform ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2005 3 0
An Efficient Implementation of Rate-Distortion Optimization for JPEG2000 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2005 0 0
AN ANALYSIS OF H.264 BASELINE PROFILE DECODER FOR REAL TIME APPLICATION ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2004 10 0
Architecture Design of DWT and Quantizer for JPEG-2000 Codec ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2003 24 0
Implementation of Hardware Simulator with Logic Analyzer and Signal Generator Function ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2003 15 0
A Mixed Mode Motion Estimation with Optimized Hardware Architectures ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2003 12 0
A MPEG-4 Video Codec Chip with Low Power Scheme for Mobile Application ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2002 15 0
An Efficient MPEG-4 Video Codec using Low-power Architectural Engines ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 2002 15 0
A Low Power Mixed Mode Motion Estimation for Data Compression 대한전자공학회 기타 간행물 2001 7 0
VHDL Modeling of a Block Data Flow Architecture for 2-D Discrete Wavelet Transform ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 1998 15 0
An Area Efficient Implementation of Zig-Zang and Quantization Buffer for H. 263 Application ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications 1998 1 0
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