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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.5
- 발행연도
- 2014.10
- 수록면
- 640 - 648 (9page)
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초록· 키워드
오류제보하기
Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS’89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.
목차
Abstract
I. INTRODUCTION
II. THE LOW SWITCHING ACTIVITY BIST SCHEME
III. THE MODIFIED FORM OF THE LSA-BIST SCHEME
IV. EXPERIMENTAL RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (26)
참고문헌 신청
1. [학술대회논문] - K. M. Butler / 2004 / Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques / IEEE Proc. ITC : 355 ~ 364
2. [학술대회논문] - J. Saxena / 2003 / A case study of IR-drop in structured at-speed testing / IEEE Proc. ITC : 1098 ~ 1104
3. [학술대회논문] - M. ElShoukry / 2005 / Partial Gating Optimization for Power Reduction during Test Application / Asian Test Symp. : 242 ~ 247
4. [학술대회논문] - Y. Yamato / 2011 / A novel scan segmentation design method for avoiding shift timing failure in scan testing / International Test Conference : 1 ~ 8
5. [학술지(정기간행물)] - Tobias Strauch / 2012 / Single Clock pulse Structure For Logic Test / IEEE transactions Very large Scale Integration (VLSI )system 20 (5) : 878 ~ 891
2. [학술대회논문] - J. Saxena / 2003 / A case study of IR-drop in structured at-speed testing / IEEE Proc. ITC : 1098 ~ 1104
3. [학술대회논문] - M. ElShoukry / 2005 / Partial Gating Optimization for Power Reduction during Test Application / Asian Test Symp. : 242 ~ 247
4. [학술대회논문] - Y. Yamato / 2011 / A novel scan segmentation design method for avoiding shift timing failure in scan testing / International Test Conference : 1 ~ 8
5. [학술지(정기간행물)] - Tobias Strauch / 2012 / Single Clock pulse Structure For Logic Test / IEEE transactions Very large Scale Integration (VLSI )system 20 (5) : 878 ~ 891
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