지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2023.9
- 수록면
- 704 - 710 (7page)
- DOI
- 10.5302/J.ICROS.2023.23.0085
이용수
이 논문의 연구 히스토리 (3)
2023
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초록· 키워드
오류제보하기
In this paper, we present a 12-bit SAR (Successive-Approximation-Register) ADC (Analog-to-Digital Converter). The proposed ADC comprises sample-and-hold, capacitor array network, SAR control logic, comparator, DAC (Digital-to-Analog Converter) control logic, and DAC stages. This SAR ADC employs a method of changing the total capacitor capacity by adding a split capacitor to the capacitor array network, because area of the capacitor and the capacitor array network increase with the increase in resolution. A sample-and-hold circuit combined with a bootstrip technique can reduce distortion and unnecessary power consumption, as this circuit is designed to operate with a single input clock. To optimize power consumption and chip area, a 1MSps sampling rate with 12-bit resolution was designed. The proposed ADC was designed using the 1poly-6 metal 0.13㎛ CMOS process, and it operates at 1.2V. A SNDR (Signal-to-Noise Distortion Ratio) and an ENOB (Effective Number of Bits) of approximately 80.09㏈ and 11.86bits, respectively ware achieved. Compared with previous research results, the effective small chip area is approximately 0.028mm2 and the low power consumption is 63.07㎼.
목차
Abstract
Ⅰ. 서론
Ⅱ. 본론
Ⅲ. 시뮬레이션 결과
Ⅳ. 주요 성능변수 평가
Ⅴ. 결론
REFERENCES
참고문헌 (25)
참고문헌 신청
J.-I. Chun, Y.-J. Choi, and J.-Y. Ryu, “Design of a low-power 12-bit 1MSps SAR analog-to-digital converter," Journal of Institute of Control, Robotics and Systems (in Korean), vol. 27, no.1, pp. 26-31, Jan. 2021.
Y.-J. Choi, J.-I. Chun, and J.-Y. Ryu, “Design of low-power programmable gain amplifier with DC-Offset cancellation circuit," Journal of Institute of Control, Robotics and Systems (in Korean), vol. 26, no. 10, pp. 832-837, Oct. 2020.
J.-I. Chun, Y.-J. Choi, E.-K. Choi, A. Siddique, M. Kurbanov, T. S. Delwar, P. Behera, M. R. Biswal, and J.-Y. Ryu, “Design of high-SNDR 12-bit 1MSps fully-differential SAR ADC," Proceedings of 2020 Symposium on the Institute of Electronics and Informatio
J.-I. Chun and J.-Y. Ryu, “A 12bit 1 Msps asynchronous Fully Differential SAR ADC for SOC," International Symposium on Precision Engineering and Sustainable Manufacturing, pp. 52, Nov. 2020.
J.-I. Chun, Y.-J. Choi, M. U Sung, A. Siddique, M. Kurbanov, T. S. Delwar, P. Behera, K.-P. Kil, S.-G. Kim, and J.-Y. Ryu, “Design of low-power 12-bit 1MSps SAR analog-to-digital converter," Proceedings of 2019 Symposium on the Institute of Electronics an
Y.-J. Choi, J.-I. Chun, and J.-Y. Ryu, “Design of low-power programmable gain amplifier with DC-Offset cancellation circuit," Journal of Institute of Control, Robotics and Systems (in Korean), vol. 26, no. 10, pp. 832-837, Oct. 2020.
J.-I. Chun, Y.-J. Choi, E.-K. Choi, A. Siddique, M. Kurbanov, T. S. Delwar, P. Behera, M. R. Biswal, and J.-Y. Ryu, “Design of high-SNDR 12-bit 1MSps fully-differential SAR ADC," Proceedings of 2020 Symposium on the Institute of Electronics and Informatio
J.-I. Chun and J.-Y. Ryu, “A 12bit 1 Msps asynchronous Fully Differential SAR ADC for SOC," International Symposium on Precision Engineering and Sustainable Manufacturing, pp. 52, Nov. 2020.
J.-I. Chun, Y.-J. Choi, M. U Sung, A. Siddique, M. Kurbanov, T. S. Delwar, P. Behera, K.-P. Kil, S.-G. Kim, and J.-Y. Ryu, “Design of low-power 12-bit 1MSps SAR analog-to-digital converter," Proceedings of 2019 Symposium on the Institute of Electronics an
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