본문 바로가기
  • 학술저널

표지

DBpia에서 서비스 중인 논문에 한하여 피인용 수가 반영됩니다. 내서재에 논문을 담은 이용자 수의 총합입니다.

초록·키워드 목차

This paper proposes a new cost-effective approximate adder that exploits OR operation and zero truncation. The proposed approximation technique reduces the hardware cost significantly while maintaining comparable computation accuracy. The proposed adder achieved 48%, 51%, and 48% reductions in the area, delay, and power, respectively, compared to a traditional adder when implemented in 32-nm CMOS technology. The proposed design could also enhance the normalized mean error distance up to 29% compare to the approximate adders considered in this paper. The adder showed an excellent tradeoff performance between the hardware and computation accuracy. Furthermore, the proposed adder was adopted in a digital image processing application, and the benefit of the proposed adder is demonstrated. #Approximate adder #Approximate computing #Low-cost #Zero truncation #Lower-part OR truncation adder (LOTA)

Abstract
1. Introduction
2. Proposed Approximate Adder
3. Experimental Results
4. Conclusions
References

저자의 논문

DBpia에서 서비스 중인 논문에 한하여 피인용 수가 반영됩니다.
Insert title here
논문의 정보가 복사되었습니다.
붙여넣기 하세요.