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    초록·키워드

    A new circuit architecture is proposed for a high speed and high accuracy sample and hold circuit that minimizes the hold step error. The high-resolution circuit is the most important aspect of A/D or D/A converters with the circuit speed. In this paper, a new sample and hold circuit that improves circuit performance - high speed and high accuracy- is proposed. The proposed sample and hold circuit operates open loop sample and hold circuit in sampling mode and closed loop sample and hold circuit in holding mode. So it acquires high speed in sampling mode and high accuracy -less dependent on the clock feedthrough- by reducing charge injection effect of MOS switch in holding mode. Moreover, with the development of multimedia and image signal processing, there are mass growth of the need of analog to digital(A/D), digital to analog(D/A) converters that have high resolutions and high conversion speed. Especially, the speed and accuracy of A/D converters are swayed by the performance of SAH circuits that transmit input signal to the A/D converters. But, there are a few limitations of the above performance and charge injections that originated in MOS switches and acts as a main noise source, degenerates the performance of the SAH circuits, because it results in nonlinearities and gain errors. There have been many ongoing researchs for this limitation and closed-loop SAH circuit has been mainly used as a compensation circuit. Though it improves the accuracy, it has a severe drawback lower the speed of the A/D converters. So closed-loop SAH circuits are not adequate for high-speed systems. In this paper, a new design method of the SAH circuits have high accuracy without degradation of speed is proposed.

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      UCI(KEPA) : I410-ECN-0101-2014-569-001015979