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    초록·키워드

    OptSizer is an automatic and optimal sizing program for CMOS combinational circuits. The input description is gate level netlists and the output is transistor netlists same as SPICE format. The three objectives - the area, delay, and product of the area and delay with weight - are formulated. The area and a fanout capacitance are estimated using a template layout for basic logic gates. A semi-empirical delay model in consideration of a slope of input waveforms gives an accurate delay value. The entire circuit is optimized at the same time. The Rosenbrock's optimization method with some modifications is used. Experimental results are showed and discussed.

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      UCI(KEPA) : I410-ECN-0101-2009-569-013167503