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    초록·키워드

    In this study, to design digital filters using Elliptic filter functions that had excellant characteristics, we have proposed a algorithm to minimize output noise and round-off error. Digital Elliptic filters was realized by PL implementation that fitted to noise characteristics, flexibility and fixed filtering for the integrated circuits(IC). After digital filters was divided into hier- archic configuration, we have performed the layout of ALU and register, a part of digital Elliptic filters. filters by procedure as follows. First, the chip configuration of digital Elliptic filters has been realized by PL(Peled-Liu) implementation after proposing digital Ellip- tic filter algorithm. Second, the hierarchic configuration of digital Elliptic filter is divided into ALU, contral, ROM and register parts according to gate volume or function. Finally,the designed 8-bit parallel ALU using ADD/SUB, D-flip flop and MSB circuit could perform ADD, SUB function, and the register designed with the 8-bit serial and parallel method could shift process. And then,its block circuits have been performed layout using CMOS 3μm role.

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      UCI(KEPA) : I410-ECN-0101-2009-569-013207180