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    초록·키워드

    Hot carrier effects in CMOS with effective gate length down to 0.1㎛ level are investigated. Hot carrier effects in 0.1㎛ level CMOS are observed at low drain voltage and its possible physical mechanisms are explained. Based on the conventional DC lifetime extrapolation technique, the maximum allowable supply voltage under DC and AC stress is extracted. The enhanced AC degradation for ultra-thin SiO₂, PMOS is explained by the hole trapping during device-off. Finally, a new method for characterizing the hot carrier degradation of ultra-thin SiO₂ PMOS is suggested.

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      UCI(KEPA) : I410-ECN-0101-2009-569-017766300