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논문 기본 정보

저자정보
(성균관대학교) (성균관대학교) (성균관대학교)
저널정보
대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
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    초록·키워드

    Existing serial scan-based BIST(Built-In Self-Test) structure causes such problems as high test power dissipation and long test application time due to serial shifting characteristics with regard to testing. The high switching activity might cause a potential damage to circuits and reduce credibility and yield of circuits. In order to resolve the problems, we propose a new RAS(Random Access Scan) architecture-based BIST structure. The structure does not implement serial shifting, so test application time and Flip-Flops switching activity are reduced. In addition, since it is BIST structure, an effective test can be realized without auxiliary test equipment. According to experimental results on ITC99 and ISCAS89, switching activity is reduced by 34.99% on average in the suggested structure compared to the serial scan architecture BIST structure.

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      UCI(KEPA) : I410-ECN-0101-2012-569-004021808