인문학
사회과학
자연과학
공학
의약학
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예술체육학
복합학
DBpia AI
AI 에이전트
AI 아이디어
AI 리더
AI 뷰어
Citeasy
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논문 기본 정보
- 저자정보
피인용 0
초록·키워드
In this paper, we present a low latency asynchronous FIFO for the interconnection between intellectual properties (IPs) in a system-on-a-chip (SoC) environment. The proposed FIFO is designed to optimize GasP [6] in a latency point of view while allowing a little less throughput than GasP because low latency is one of the most important required performance factors of asynchronous FIFOs used for SoC. We designed a pre-layout of HSPICE simulations under 8-stage FIFO with 16-bit datapath and compared its performance with that of GasP. The simulation shows that the proposed FIFO gave 2.75 GHz throughput in Anam’s 0.25 μm technology and improved latency of GasP by 18.6%. Even, synchronization problem cannot occur whilst interconnecting previous IPs in order for designers easily to combine them. Meanwhile, the asynchronous design method essentially requires asynchronous FIFOs between two modules to interconnect IPs. The asynchronous FIFO is an asynchronous module that interconnects the two IPs or modules in order to communicate each other. The advantages of asynchronous FIFOs include the elastic data rate of input and output stage, a low latency and high throughput rate, which improve the whole system performance. Low latency and high throughput are the most important factors in the asynchronous FIFO design for designers to consider. In this paper, we propose an improved FIFO which has a lower latency than GasP. The rest of the paper is organized as follows. Section 2 briefly introduces the concept of asynchronous design and previous related work of asynchronous FIFOs. Section 3 then introduces the proposed FIFO. Section 4 provides pre-layout simulation results, whilst section 5 finally discusses conclusion and future work.
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최근 본 자료 전체보기
UCI(KEPA) : I410-ECN-0101-2013-569-001088247
