인문학
사회과학
자연과학
공학
의약학
농수해양학
예술체육학
복합학
DBpia AI
AI 에이전트
AI 아이디어
AI 리더
AI 뷰어
Citeasy
크롬 서지관리 다운로드
지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 IEIE Transactions on Smart Processing & Computing IEIE Transactions on Smart Processing & Computing Vol.4 No.4
- 발행연도
- 2015.8
- 수록면
- 237 - 250 (14page)
이용수
초록· 키워드
This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries’ speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but highperformance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.
#Advanced driver assistance systems (ADAS)
#Speed limit traffic sign detection
#Rectangle pattern matching
#Circle detection
#FPGA implementation
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목차
- Abstract
- 1. Introduction
- 2. Image Size and Scan Window Size Requirement for SLT Sign Detection
- 3. Related Works
- 4. Rough and Simple Feature Combination for Real-Time SLTSR Systems
- 5. Hardware Implementation
- 6. Evaluation Results and Discussion
- 7. Conclusion
- References
참고문헌
참고문헌 신청최근 본 자료
UCI(KEPA) : I410-ECN-0101-2016-569-001875115
