인문학
사회과학
자연과학
공학
의약학
농수해양학
예술체육학
복합학
DBpia AI
AI 에이전트
AI 아이디어
AI 리더
AI 뷰어
Citeasy
크롬 서지관리 다운로드
지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 저자정보
피인용 0
초록·키워드
At SK hynix’s wafer level package (WLPKG) line, a passivation SiN layer is deposited to prevent Cu diffusion in through silicon via (TSV), followed by a tetraethyl orthosilicate (TEOS)-based SiO₂ layer deposition to ensure TSV robustness during planarization of protruded TSVs. With the increasing demand for high bandwidth memory (HBM), the TEOS SiO₂ deposition process became a throughput bottleneck due to the chamber configuration of the existing CVD equipment. To enhance productivity, process optimization was pursued to improve the deposition rate while maintaining the film properties required for subsequent processes. Recipe modifications were evaluated under mass production conditions, with a focus on deposition rate, film uniformity, and potential risks such as particle generation and CMP removal rate (R/R) changes that could impact TSV yield. Increasing TEOS flow initially improved the deposition rate by up to 78% but caused TSV damage due to higher CMP R/R at wafer edges. By optimizing O₂ flow, He-carrier flow, and chamber pressure, film robustness was enhanced, and final adjustments reduced TEOS flow to achieve a 46% rate improvement without significant R/R variation. The optimized recipe increased CVD process capacity by approximately 25%, meeting both productivity and quality stability requirements for high-volume HBM manufacturing.
본문·목차
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