인문학
사회과학
자연과학
공학
의약학
농수해양학
예술체육학
복합학
DBpia AI
AI 에이전트
AI 아이디어
AI 리더
AI 뷰어
Citeasy
크롬 서지관리 다운로드
지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 저자정보
피인용 0
초록·키워드
Artificial neural networks have recently been widely used in image classification, object detection, and character recognition. However, the amounts of learning and computation in the model required to achieve high accuracy have increased rapidly. As a result, a bottleneck phenomenon has intensified. Research on approaches such as reducing the weights models and optimizing calculations are being conducted to solve this problem. Binary neural networks are receiving significant attention for field-programmable gate array (FPGA)-based designs owing to their high computational efficiency and low-power designs. In this paper, we propose a binary neural network with an FPGA-based low-power accumulator. Based on the hardware resource consumption of each layer, operations are optimized by targeting more hardware-intensive layers. In addition, we propose a new method for operating the accumulator for adding the existing operation results during the learning process in the neural networks. As a result, a binary neural network using the optimized accumulator reduces power by up to 55% compared to the previous network; the other hardware usage was also reduced by 27%. Nevertheless, the delay time remains constant, and the accuracy remains at 90%.
본문·목차
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UCI(KEPA) : I410-151-26-02-094678569
