인문학
사회과학
자연과학
공학
의약학
농수해양학
예술체육학
복합학
DBpia AI
AI 에이전트
AI 아이디어
AI 리더
AI 뷰어
Citeasy
크롬 서지관리 다운로드
지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 저자정보
피인용 0
초록·키워드
We present a 64-channel implantable neural stimulator with sub-nC charge-balanced current stimulation for seizure suppression applications. The regulated cascode current driver achieves almost full VDD compliance voltage range with 98% supply voltage utilization (4.9V from 5V) in standard 0.18 mm CMOS technology, eliminating
the need for expensive high-voltage processes. A passive charge balancing scheme using a bootstrapped switch with reduced on-resistance (19.56 W) maintains residual charge levels below 1 nC, well within the 15 nC safe limits, enabling reliable long-term operation. The stimulation parameters, including current pulse width (1 ms-1023 ms), channel activation, stimulation frequency, and current amplitude (1 mA to 1.8 mA), are highly reconfigurable through a 10 MHz SPI interface, enabling real-time adaptive stimulation protocols. The hierarchical 8+3-bit DAC architecture provides superior current resolution compared to existing single DAC systems while maintaining compact area efficiency of 0.0125 mm² per channel. In-vivo animal experiments demonstrate effective seizure suppression, achieving seizure reduction within 14 seconds after 40 seconds of 5 Hz stimulation at 50 mA amplitude, validating the therapeutic efficacy of the proposed system. The fabricated IC in 0.18 mm standard CMOS process successfully combines high channel count, optimal compliance voltage utilization, enhanced safety margins, and in-vivo validation, making it suitable for practical implantable epilepsy treatment applications.
the need for expensive high-voltage processes. A passive charge balancing scheme using a bootstrapped switch with reduced on-resistance (19.56 W) maintains residual charge levels below 1 nC, well within the 15 nC safe limits, enabling reliable long-term operation. The stimulation parameters, including current pulse width (1 ms-1023 ms), channel activation, stimulation frequency, and current amplitude (1 mA to 1.8 mA), are highly reconfigurable through a 10 MHz SPI interface, enabling real-time adaptive stimulation protocols. The hierarchical 8+3-bit DAC architecture provides superior current resolution compared to existing single DAC systems while maintaining compact area efficiency of 0.0125 mm² per channel. In-vivo animal experiments demonstrate effective seizure suppression, achieving seizure reduction within 14 seconds after 40 seconds of 5 Hz stimulation at 50 mA amplitude, validating the therapeutic efficacy of the proposed system. The fabricated IC in 0.18 mm standard CMOS process successfully combines high channel count, optimal compliance voltage utilization, enhanced safety margins, and in-vivo validation, making it suitable for practical implantable epilepsy treatment applications.
본문·목차
인공지능 문자 인식 모델을 통해 추출된 텍스트로, 일부 오타나 오류가 포함될 수 있으나 지속적으로 개선 중입니다.
오류를 발견하셨다면 해당 부분을 드래그한 후 ' 를 통해 신고해주세요.
오류를 발견하셨다면 해당 부분을 드래그한 후 ' 를 통해 신고해주세요.
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UCI(KEPA) : I410-151-26-02-094677124
