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논문 기본 정보

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대한전자공학회 IEIE Transactions on Smart Processing & Computing IEIE Transactions on Smart Processing & Computing Vol.15 No.4
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    초록·키워드

    In this paper, we propose a novel hardware architecture specifically designed to enable real-time response in disaster environments, where rapid decision-making and low-latency processing are critical. Our approach focuses on optimizing a GAN-based radar voice imaging system, which processes radar signals and generates visual representations in real time. To enhance accuracy and robustness, we developed a simulation framework that assigns dynamic weights to each incoming signal, enabling the system to identify the signal path with the minimum loss through iterative optimization. The proposed architecture was implemented using Register-Transfer Level (RTL) coding, targeting efficient hardware utilization while maintaining high-speed operation. To validate the design, we conducted logic synthesis and timing verification using the Xilinx Vivado<sup>R</sup> synthesis environment. This step ensured that the proposed system not only met functional correctness but also satisfied timing and area constraints required for deployment in edge computing scenarios, such as portable disaster response units. The synthesis results demonstrated that the design is highly resource-efficient, consuming only 2% of available Look-Up Tables (LUTs), 2% of flip-flops (FFs), 13% of input/output (I/O) resources, and 1% of global clock buffers (BUFGs). These results indicate the architecture’s suitability for integration into FPGA-based platforms with limited hardware resources, offering a practical solution for real-time radar signal processing in critical field applications.

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