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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전기학회 Journal of Electrical Engineering & Technology Journal of Electrical Engineering & Technology Vol.13 No.4
- 발행연도
- 2018.7
- 수록면
- 1,425 - 1,437 (13page)
이용수
초록· 키워드
In this paper, a methodology was proposed to reduce the electrical level and spatial size of the smart grid with distributed generations (DGs) to a scale in which the electrical phenomena and control strategies for disturbances on the smart grid could be safely and freely experimented and observed. Based on the design methodology, a micro smart grid simulator with a substation transformer capacity of 190VA, voltage level of 19V, maximum breaking current of 20A and size of 2 x 2 ㎡ was designed by reducing the substation transformer capacity of 45MVA, voltage level of 23kV and area of 2 x 2 k㎡ of the smart grid to over one thousandth, and also reducing the maximum breaking current of 12kA of the smart grid to 1/600. It was verified that the proposed design methodology and designed micro smart grid simulator were very effective by identifying how all of the fault currents are limited to within the maximum breaking current of 20A, and by confirming that the maximum error between the fault currents obtained from the fault analysis method and the simulation method is within 1.8% through the EMTP-RV simulation results to the micro smart grid simulator model.
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목차
- Abstract
- 1. Introduction
- 2. FCL Design Methodology of Smart Grid
- 3. Design of Micro Smart Grid Simulator
- 4. Validation of the Design Methodology
- 5. Conclusions
- References
참고문헌
참고문헌 신청최근 본 자료
UCI(KEPA) : I410-ECN-0101-2018-560-002230515
