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자료유형
학술저널
저자정보
(Raja College of Engineering and Technology) (Thiagarajar College of Engineering)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.14 No.1
발행연도
수록면
48 - 60 (13page)

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초록· 키워드

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.
#Modulation Index (MI) #Unipolar Sinusoidal Pulse Width Modulation (USPWM) #Saw Tooth Multicarrier USPWM (STMC USPWM) #Total Harmonic Distortion (THD) #Triangular Multicarrier USPWM (TMC USPWM) #Unipolar Sine Multicarrier USPWM (USMC USPWM)
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목차

  1. Abstract
  2. Ⅰ. INTRODUCTION
  3. Ⅱ. CONVENTIONAL CASCADED MULTILEVEL INVERTER
  4. Ⅲ. PROPOSED REDUCED SWITCH CASCADED MULTILEVEL INVERTER TOPOLOGY
  5. Ⅳ. MODULATION TECHNIQUES
  6. Ⅴ. SIMULATION RESULTS
  7. Ⅵ. EXPERIMENTAL RESULTS
  8. Ⅶ. CONCLUSION
  9. REFERENCES

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UCI(KEPA) : I410-ECN-0101-2015-500-000998501