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자료유형
학술저널
저자정보
(Inha University) (Inha University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.1
발행연도
수록면
118 - 125 (8page)

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초록· 키워드

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.
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목차

  1. Abstract
  2. Ⅰ. INTRODUCTION
  3. Ⅱ. BACKGROUND
  4. Ⅲ. MODIFIED LOPEZ-DAHAB AND LEFT-TORIGHT ALGORITHM
  5. Ⅳ. PROPOSED ECC POINT MULTIPLICATION ARCHITECTURE
  6. Ⅴ. RESULTS AND COMPARISON
  7. Ⅵ. CONCLUSION
  8. REFERENCES

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