메뉴 건너뛰기
소속 기관 / 학교 인증
인증하면 논문, 학술자료 등을  무료로 열람할 수 있어요.
한국대학교, 누리자동차, 시립도서관 등 나의 기관을 확인해보세요
(국내 대학 90% 이상 구독 중)
고객센터 ENG
주제분류

논문 기본 정보

저자정보
(Chonnam National University) (Mokpo National University) (Chonnam National University) (Chonnam National University) (Seoul National University) (The KEPCO Research Institute) (Seoul National University) (Chonnam National University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.5
오류 신고하기

피인용 0

검색

    초록·키워드

    The FN-tunneling gate-current model for the three-dimensional recessed-channel structure including a geometrical effect is obtained. Further, the measurement results in the fabricated 60-nm DRAM chip are well fitted using our modeled simulation results in consideration of the cylindrical coordinate and the poly-depletion effect. As the recessed structure was scaled down to sub-50-nm technology with a very thin oxide thickness and a small radius, for which the reliability issues were considered, the geometrical effect seriously affected the memory-sensing margin. Our model presents a sound solution for the attainment of a fast and accurate FN-tunneling gate current to resolve the reliability issues of memory-cell transistors.

    최근 본 자료 전체보기