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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.1
- 발행연도
- 2019.2
- 수록면
- 69 - 78 (10page)
- DOI
- 10.5573/JSTS.2019.19.1.069
이용수
초록· 키워드
오류제보하기
We fabricated and characterized the double-gate (DG) charge-trap memory thin film transistors (CTM-TFTs) using In-Ga-Zn-O active and ZnO charge-trap layers. The fabricated device exhibited a charge-trap-assisted memory window as wide as 13.8 V using a DG mode operation and a program/erase (P/E) speed faster than 10 μs. These memory device characteristics were examined by controlling the fixed bias voltage applied at the bottom gate (V<SUB>BG</SUB>) and the capacitance coupling ratio between top and bottom gate insulators, which could be strategically designed with the DG configuration. The capacitance coupling ratio was varied by changing the bottom gate insulator (BGI) thickness between 50 and 100 nm. For the CTM-TFT with a BGI thickness of 100 nm, 3.1×10<SUP>6</SUP> was obtained for the memory on/off ratio with P/E voltages of ± 15 V and a fixed V<SUB>BG</SUB> of -3 V. Overall, our results suggest that the DG configuration can remarkably enhance the P/E speed and memory on/off ratio by suitably controlling the fixed V<SUB>BG</SUB> conditions and the capacitance coupling ratio in CTM-TFTs.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. DEVICE FABRICATION
Ⅲ. MEMORY DEVICE CHARACTERIZATION
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (24)
참고문헌 신청
K. Nomura, et al, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, Vol. 432, pp. 488-492, Oct. 2004.
C. Zhao, et al, “Two-dimensional numerical simulation of bottom-gate and dual-gate amorphous In-Ga-Zn-O MESFETs,” IEEE Electron Device Lett., Vol. 35, No. 1, pp. 75-77, Jan. 2014.
X. He, et al, “Implementation of fully self-aligned homojunction double-gate a-IGZO TFTs,” IEEE Electron Device Lett., Vol. 35, No. 9, pp. 927-929, Sep. 2014.
S. Y. Lee, “Improvement on the stability of amorphous indium gallium zinc oxide thin film transistors using amorphous oxide multilayer source/drain electrodes,” Trans. Elect. Electron. Mater., Vol. 17, No. 6, pp. 143-145, Jun. 2016.
S. H. Nam, et al, “NOT and NOR logic circuits using passivation dielectric involved dual gate in a- InGaZnO TFTs,” IEEE Electron Device Lett., Vol. 34, No. 12, pp. 1527-1529, Dec. 2013.
C. Zhao, et al, “Two-dimensional numerical simulation of bottom-gate and dual-gate amorphous In-Ga-Zn-O MESFETs,” IEEE Electron Device Lett., Vol. 35, No. 1, pp. 75-77, Jan. 2014.
X. He, et al, “Implementation of fully self-aligned homojunction double-gate a-IGZO TFTs,” IEEE Electron Device Lett., Vol. 35, No. 9, pp. 927-929, Sep. 2014.
S. Y. Lee, “Improvement on the stability of amorphous indium gallium zinc oxide thin film transistors using amorphous oxide multilayer source/drain electrodes,” Trans. Elect. Electron. Mater., Vol. 17, No. 6, pp. 143-145, Jun. 2016.
S. H. Nam, et al, “NOT and NOR logic circuits using passivation dielectric involved dual gate in a- InGaZnO TFTs,” IEEE Electron Device Lett., Vol. 34, No. 12, pp. 1527-1529, Dec. 2013.
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UCI(KEPA) : I410-ECN-0101-2019-569-000425960