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논문 기본 정보

자료유형
학술저널
저자정보
(Ton Duc Thang University) (Inha University) (Inha University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.2
발행연도
수록면
220 - 223 (4page)
DOI
10.5573/JSTS.2020.20.2.220

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초록· 키워드

This paper presents a novel architecture to perform polynomial multiplication in ring learning with errors (ring-LWE) cryptosystems. By employing number theoretic transform (NTT) of the input polynomials simultaneously, the multiplication latency is significantly reduced. In addition, a multiple-path delay feedback (MDF) architecture is used to speed up the multiplication process. As a result, the proposed NTT multiplier offers a better value of area-latency product compared with that of previous studies. The simulation results for the security parameters n = 512 and q = 12,289 on Xilinx Virtex-7 FPGA show that the proposed multiplier uses only about 8.69% of the number of clock cycles required by previous works to completely perform the polynomial multiplication. Furthermore, the obtained area-latency product value of the proposed architecture is less than 45.3% of that of previous works.
#Cryptography #multiple-path delay feedback #NTT polynomial multiplier #ring-LWE
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목차

  1. Abstract
  2. I. INTRODUCTION
  3. II. PROPOSED NTT POLYNOMIAL MULTIPLIER
  4. III. RESULTS AND COMPARISONS
  5. IV. CONCLUSIONS
  6. REFERENCES

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UCI(KEPA) : I410-ECN-0101-2020-569-000585144