인문학
사회과학
자연과학
공학
의약학
농수해양학
예술체육학
복합학
DBpia AI
AI 에이전트
AI 아이디어
AI 리더
AI 뷰어
Citeasy
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지원사업
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커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
피인용 0
초록·키워드
Recently, the flash memory has been abstracting great attention in the semiconductor market in the world because of its potential applications as mass storage devices. One of the most significant barriers to the scaling-down of the stacked-gate devices such as EPROM's and flash EEPROM's is the large subthreshold leakage in the unselected cells connected with the bit line of a selected cell in the array during programming. The large subthreshold leakage is majorly due to the capacitive coupling between the floating gates of the unselected cells and the bit line of selected cell. In this paper, a new programming method to reduce significantly the drain turn-on leakage in the unselected cells during programming has been studied, where a little positive voltage (0.25-0.75V) is applied to the source during programming unlike the conventional programming method in which the source is grounded. The results of the PISCES simulations and the electrical measurements for the standard EPROM with 0.35μm effective channel length and 1.0μm effective channel width show that the subthreshold leakage in the unselected cells is significantly large when the source is grounded, whereas it is negligibly small when the source is biased to a little positive voltage during programming. On the other hand, the positive bias on the source is found to have little effects on the programming speed of the EPROM.
본문·목차
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UCI(KEPA) : I410-ECN-0101-2009-569-013275531
