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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.7 No.2
- 발행연도
- 2007.6
- 수록면
- 67 - 75 (9page)
이용수
초록· 키워드
To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with freelevel precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negativelydriven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.
#DRAM
#charge-transferred presensing(CTPS)
#negatively-driven sensing(NDS)
#free-level precharged bitline(FLPB)
#sense amplifier offset voltage
#threshold voltage distribution
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목차
- Abstract
- Ⅰ. INTRODUCTION
- Ⅱ. CHARGE-TRANSFERRED PRESENSING (CTPS) AND CONVENTIONAL SENSING SCHEME
- Ⅲ. NEGATIVELY DRIVEN SENSING (NDS) AND FREE-LEVEL PRECHARGED BITLINE (FLPB) SCHEME
- Ⅳ. A SENSE AMPLIFIER OFFSET CANCELLATION SCHEME AND MEASURED RESULTS
- Ⅴ. CONCLUSIONS
- REFERENCES
참고문헌
참고문헌 신청최근 본 자료
UCI(KEPA) : I410-ECN-0101-2009-569-016815899
