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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.11 No.4
- 발행연도
- 2011.12
- 수록면
- 262 - 271 (10page)
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초록· 키워드
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In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. THE MODEL
Ⅲ. RESULTS
Ⅳ. SUMMARY AND CONCLUSION
REFERENCES
참고문헌 (11)
참고문헌 신청
1. [학술지(정기간행물)] - 최양규 / 200109 / Nanoscale ultrathin body PMOSFETs with raised selective germanium source/drain / IEEE ELECTRON DEVICE LETTERS 22 (9) : 447 ~ 448
2. [학술지(정기간행물)] - J.P. Colinge / 1986 / Subthreshold slope of thin-film SOI MOSFETs / IEEE Electron Device Letters 7 (4) : 244 ~ 246
3. [학술지(정기간행물)] - H. Lim / 1983 / Threshold voltage of thin-film Silicon-on-Insulator (SOI) MOSFETs / IEEE Transactions on Electron Devices 30 (10) : 1244 ~ 1251
4. [학술지(정기간행물)] - Y.S. Yu / 2005 / All analytic surface potential model for SOI MOSFETs / IEE Proceedings - Circuits, Devices and Systems 152 (2) : 183 ~ 188
5. [학술지(정기간행물)] - J.W. Sleight / 1998 / A continuous compact MOSFET model for fully and partially-depleted SOI devices / IEEE Transactions on Electron Devices 45 (4) : 821 ~ 825
2. [학술지(정기간행물)] - J.P. Colinge / 1986 / Subthreshold slope of thin-film SOI MOSFETs / IEEE Electron Device Letters 7 (4) : 244 ~ 246
3. [학술지(정기간행물)] - H. Lim / 1983 / Threshold voltage of thin-film Silicon-on-Insulator (SOI) MOSFETs / IEEE Transactions on Electron Devices 30 (10) : 1244 ~ 1251
4. [학술지(정기간행물)] - Y.S. Yu / 2005 / All analytic surface potential model for SOI MOSFETs / IEE Proceedings - Circuits, Devices and Systems 152 (2) : 183 ~ 188
5. [학술지(정기간행물)] - J.W. Sleight / 1998 / A continuous compact MOSFET model for fully and partially-depleted SOI devices / IEEE Transactions on Electron Devices 45 (4) : 821 ~ 825
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