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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 207 - 210 (4page)
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초록· 키워드
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Identification of inefficiencies in some parts of conventional processor mechanism and its countermeasure are required in order to tackle conflicting design requirement in embedded system processors design. In this paper, we proposed a novel architecture which combines large entry of Instruction Register along with unique binary translation to aim more efficient fetch mechanism that leads to further reduction of processor’s code size. From simulation result, we found that the proposed method succeeded in reducing code size significantly compared to conventional processor.
목차
Abstract
1. INTRODUCTION
2. I-FETCH INEFFICIENCIES AND INSTRUCTION REGISTER
3. EMPLOYING LARGE ENTRY OF IR AND ITS ADVANTAGE
4. PROPOSED METHOD
5. EXPERIMENTAL RESULTS
6. RELATED WORKS
7. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001474767