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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2010.11
- 수록면
- 424 - 427 (4page)
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초록· 키워드
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In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant impacts on gain, bandwidth, noise, stability, and area of the patch-clamp amplifier, in this work, we present the design analysis for the TIA and its optimal feedback resistance. The proposed patch-clamp amplifier has a maximum gain of 152.2dBΩ, an input-referred noise of 11.3pA<SUB>RMS</SUB> within bandwidth of 10 KHz, and occupies an active die-area of 0.0625㎟. This amplifier is under fabrication in a 0.35μm CMOS 4M2P Process.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PATCH-CLAMP AMPLIFIER ARCHITECTURE
Ⅲ. DESIGN ANALYSIS OF TIA
Ⅳ. CIRCUIT IMPLEMENTATION OF TIA
Ⅴ. POST-LAYOUT SIMULATION RESULTS
Ⅵ. CONCLUSION
ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001489866