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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 317 - 320 (4page)
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초록· 키워드
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Reducing energy consumption is an important problem in the embedded system design, and especially, the leakage energy reduction has now become crucial. In order to reduce the leakage energy, power gating is a promising technique which realizes partial power shutdown at standby time. However, the power gating usually causes performance and energy overheads, and this makes the instruction scheduling complicated. In this paper, we propose energy-aware SA-based instruction scheduling for fine-gained power-gated VLIW processors as fast and accurate instruction scheduling. The experimental results show that the proposed instruction scheduling outputs almost optimal results such that the error between the optimal scheduling is less than 5%. The calculation time to perform the scheduling is also drastically reduced by 95 times than the LP solver.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. FINE-GRAINED POWER-GATED VLIW PROCESSOR MODEL
Ⅲ. SA-BASED INSTRUCTION SCHEDULING
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSION AND FUTURE WORK
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000729809