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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 417 - 420 (4page)
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초록· 키워드
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In this paper, parallel and digit-serial implementations of area-efficient 3-operand decimal adders are proposed. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient additions with three operands. Unit gate estimates and synthesis results show that our proposed adders are more area-efficient than those previously proposed decimal adders with three operands under the same delay constraints. Also the power consumptions for our decimal adders are lesser. In addition to parallel implementations, the digit-serial 3-operand adders are easily developed to increase the throughput and the operating frequency due to area efficiency. Our proposed decimal adders could be applied to ease the tremendous computation efforts for decimal computations such as multi-operand decimal additions, decimal multiplications and divisions.
목차
Abstract
Ⅰ. INTRODUCTION (HEADING 1)
Ⅱ. PREVIOUS PROPOSED 3-OPERAND DECIMAL ADDERS
Ⅲ. PROPOSED AREA-EFFICIENT 3-OPERAND DECIMAL ADDERS
Ⅳ. CMOS VLSI IMPLEMENTATION RESULTS AND COMPARISONS
Ⅴ. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000730051