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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2014.1
- 수록면
- 48 - 60 (13page)
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Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CONVENTIONAL CASCADED MULTILEVEL INVERTER
Ⅲ. PROPOSED REDUCED SWITCH CASCADED MULTILEVEL INVERTER TOPOLOGY
Ⅳ. MODULATION TECHNIQUES
Ⅴ. SIMULATION RESULTS
Ⅵ. EXPERIMENTAL RESULTS
Ⅶ. CONCLUSION
REFERENCES
참고문헌 (28)
참고문헌 신청
1. [학술지(정기간행물)] - K. Jang-Hwan / 2008 / A carrier-based PWM method with optimal switching sequence for a multilevel four-leg voltage source inverter / IEEE Trans. Ind. Appl 44 (4) : 1239 ~ 1248
2. [학술지(정기간행물)] - S. Srikanthan / 2010 / DC capacitor voltage equalization in neutral clamped inverters for DSTATCOM application / IEEE Trans. Ind. Electron 57 (8) : 2768 ~ 2775
3. [학술지(정기간행물)] - L. M. Tolbert / 1999 / Multilevel converters for large electric drives / IEEE Trans. Ind. Appl 35 (1) : 36 ~ 44
4. [학술지(정기간행물)] - P.Bhagwat / 1983 / Generalized structure of a multilevel PWM Inverter / IEEE Trans. Ind. Appln 1A-19 (6) : 1057 ~ 1069
5. [학술대회논문] - R. H. Osman / 1999 / A medium-voltage drive utilizing series-cell multilevel topology for outstanding power quality / Conf. Rec. 34th IEEE IAS Annu. Meeting 4 : 2662 ~ 2669
2. [학술지(정기간행물)] - S. Srikanthan / 2010 / DC capacitor voltage equalization in neutral clamped inverters for DSTATCOM application / IEEE Trans. Ind. Electron 57 (8) : 2768 ~ 2775
3. [학술지(정기간행물)] - L. M. Tolbert / 1999 / Multilevel converters for large electric drives / IEEE Trans. Ind. Appl 35 (1) : 36 ~ 44
4. [학술지(정기간행물)] - P.Bhagwat / 1983 / Generalized structure of a multilevel PWM Inverter / IEEE Trans. Ind. Appln 1A-19 (6) : 1057 ~ 1069
5. [학술대회논문] - R. H. Osman / 1999 / A medium-voltage drive utilizing series-cell multilevel topology for outstanding power quality / Conf. Rec. 34th IEEE IAS Annu. Meeting 4 : 2662 ~ 2669
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