지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.1
- 발행연도
- 2014.2
- 수록면
- 131 - 137 (7page)
이용수
초록· 키워드
오류제보하기
A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of 1385 × 835 μm².
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CIRCUIT DESIGN
Ⅲ. MEASUREMENT
Ⅳ. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
1. [학술대회논문] - D. Huang / 2008 / 324GHz CMOS Frequency Generator Using Linear Superposition Technique / IEEE International Solid-State Circuits Conference : 476 ~ 629
2. [학술대회논문] - E. Seok / 2008 / A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna / IEEE International Solid-State Circuits Conference : 472 ~ 629
3. [학술대회논문] - A. Tang / 2012 / D-band frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS technology / IEEE MTT-S International Microwave Symposium Digest : 1 ~ 3
4. [학술대회논문] - W.-Z. Chen / 2012 / A 160-GHz receiverbased phase-locked loop in 65 nm CMOS technology / Symposium on VLSI Circuits : 12 ~ 13
5. [학술지(정기간행물)] - K. -H. Tsai / 2012 / A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency / IEEE Transactions on Very Large Scale Integration Systems 20 : 80 ~ 88
2. [학술대회논문] - E. Seok / 2008 / A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna / IEEE International Solid-State Circuits Conference : 472 ~ 629
3. [학술대회논문] - A. Tang / 2012 / D-band frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS technology / IEEE MTT-S International Microwave Symposium Digest : 1 ~ 3
4. [학술대회논문] - W.-Z. Chen / 2012 / A 160-GHz receiverbased phase-locked loop in 65 nm CMOS technology / Symposium on VLSI Circuits : 12 ~ 13
5. [학술지(정기간행물)] - K. -H. Tsai / 2012 / A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency / IEEE Transactions on Very Large Scale Integration Systems 20 : 80 ~ 88
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2015-560-001276479