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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 1 - 4 (4page)
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초록· 키워드
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In TSV (Through-Silicon-Via) based 3D ICs, synthesizing 3D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, FFs) through TSVs, any fault on a TSV in the clock tree causes a chip failure. Therefore, ensuring the reliability of clock TSVs is highly important. Instead of the naive solution using double-TSV technique, which demands significant area overhead because of the large size of TSV, a structure called TSV fault-tolerant unit is proposed to provide TSV fault tolerance with minimum area overhead. In this work, we analyze a set of diverse structures of clock TSV fault-tolerant units which include not only the existing ones but also possible variants we devised, with respect to the TSV fault coverage and resource overhead such as additional TSVs, gates, and wires required. Our analysis results can be used usefully to provide designers with a guideline on the selection of TSV fault-tolerant unit that is best suited for their 3D IC design objectives and constraints.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. EXISTING TSV FAULT-TOLERANT STRUCTURES
Ⅲ. VARIANTS OF TSV FAULT-FAULT TOLERANT STRUCTURES
Ⅳ. EXPERIMENTAL RESULTS
Ⅴ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2016-569-001048296