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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2012.9
- 수록면
- 265 - 273 (9page)
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초록· 키워드
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Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.
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참고문헌 (15)
참고문헌 신청
1. [학술지(정기간행물)] - K. Takeda / 2006 / A read-static- noise-margin-free SRAM cell for low-VDD and high-speed applications / IEEE Journal of Solid-State Circuits 41 : 113 ~ 121
2. [학술대회논문] - L. Chang / 2005 / Stable SRAM cell design for the 32 nm node and beyond / in Symposium on VLSI Technology, Japan : 128 ~ 129
3. [학술지(정기간행물)] - N. Verma / 2008 / A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy / IEEE Journal of Solid-State Circuits 43 : 141 ~ 149
4. [학술지(정기간행물)] - L. Chang / 2008 / An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches / IEEE Journal of Solid-State Circuits 43 : 956 ~ 963
5. [학술지(정기간행물)] - Z. Liu / 2008 / Characterization of a novel nine-transistor SRAM cell / IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 : 488 ~ 492
2. [학술대회논문] - L. Chang / 2005 / Stable SRAM cell design for the 32 nm node and beyond / in Symposium on VLSI Technology, Japan : 128 ~ 129
3. [학술지(정기간행물)] - N. Verma / 2008 / A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy / IEEE Journal of Solid-State Circuits 43 : 141 ~ 149
4. [학술지(정기간행물)] - L. Chang / 2008 / An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches / IEEE Journal of Solid-State Circuits 43 : 956 ~ 963
5. [학술지(정기간행물)] - Z. Liu / 2008 / Characterization of a novel nine-transistor SRAM cell / IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 : 488 ~ 492
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