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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.17 No.2
- 발행연도
- 2017.4
- 수록면
- 239 - 244 (6page)
이용수
초록· 키워드
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We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source (V<SUB>GS</SUB>) and drain-to-source (V<SUB>DS</SUB>) bias stresses of (VGS = 24 V, VDS = 15.9 V) and (V<SUB>GS</SUB> = 22 V, V<SUB>DS</SUB> = 20 V), but the asymmetrical degradation is more significant after the bias stress (V<SUB>GS</SUB>, V<SUB>DS</SUB>) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress (V<SUB>GS</SUB>, V<SUB>DS</SUB>) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance (R<SUB>S</SUB>) and the voltage drop at R<SUB>S</SUB> (V<SUB>S</SUB>, <SUB>drop</SUB>) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and V<SUB>S</SUB>, <SUB>drop</SUB> are extracted under the bias stress (V<SUB>GS</SUB>, V<SUB>DS</SUB>) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.
목차
Abstract
I. INTRODUCTION
II. DEVICE FABRICATION
III. RESULTS AND DISCUSSION
IV. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (11)
참고문헌 신청
K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, pp. 488?492, Nov. 2004.
T. Arai, “Oxide-TFT technologies for nextgeneration AMOLED displays,” J. Soc. Info. Display, vol. 20, pp. 156?161, Mar. 2012.
S. Oh, J. H. Baeck, H. S. Shin, J. U. Bae, K.-S. Park, and I. B. Kang, “Comparison of top-gate and bottom-gate amorphous InGaZnO thin-film transistors with the same SiO2/a-InGaZnO/SiO2 stack,” IEEE Electron Device Lett., vol. 35, pp. 1037?1039, Oct. 2014.
X. Li, D. Geng, M. Mativenga, and J. Jang, “Highspeed dual-gate a-IGZO TFT-based circuits with top-gate offset structure,” IEEE Electron Device Lett., vol. 35, pp. 461?463, Apr. 2014.
J. P. Lee, J. Y. Hwang, and B. S. Bae, “Pixel Circuits with Threshold Voltage Compensation using a-IGZO TFT for AMOLED,” J. Semicond. Tech. Sci., vol. 14, pp.594-600, Oct., 2014.
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