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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 IEIE Transactions on Smart Processing & Computing IEIE Transactions on Smart Processing & Computing Vol.6 No.5
- 발행연도
- 2017.10
- 수록면
- 347 - 354 (8page)
- DOI
- 10.5573/IEIESPC.2017.6.5.347
이용수
초록· 키워드
In this paper, hardware acceleration using a field programmable gate array is proposed to provide low development–cost and high-performance stream processing hardware. This research is proposed as an enhancement to the software-based application for frequent item counting (FIC) and to contribute to hardware-based FIC for hardware/software co-design. We design an experiment by taking advantage of high-level synthesis (HLS) and the heterogeneous Computing Oriented Development Environment (hCODE), an open source platform providing a methodology and a tool for scalable and portable Internet Protocol design. The proposed scheme considers optimization techniques offered by HLS compilers, such as the pipeline technique, loop unrolling, and memory partition. Our implementation shows that the proposed scheme achieves a better overall performance than a software scheme, and more importantly, introduces fast and low development costs for hardware accelerators.
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목차
- Abstract
- 1. Introduction
- 2. Related Works
- 3. FIC Software Implementation
- 4. Proposed FIC Hardware
- 5. System Architecture
- 6. Evaluation
- 7. Conclusion
- References
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