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자료유형
학술저널
저자정보
(Ulsan National Institute of Science and Technology) (Kwangwoon University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.18 No.4
발행연도
수록면
461 - 467 (7page)
DOI
10.5573/JSTS.2018.18.4.461

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초록· 키워드

In this paper, a novel sandwiched-gate logic family that is based on a sandwiched-gate inverter, which consists of an NMOS Gate-All-Around (GAA) together with a donut-type PMOS GAA, is proposed. For the realization of the proposed vertical structure, a junctionless configuration is suggested with the absence of the channel- doping process. The ratio of the thickness of the NMOS and the PMOS determines the switching threshold in the sandwiched-gate inverter. The direct-current (DC) operation and the transient performance of the sandwiched-gate inverter are investigated with 3D technology computer-aided-design (TCAD) simulations. The sandwiched- gate inverter exhibits a correct inverter operation with a high noise margin and a fast transition speed. To extend the proposed architecture to other logic gates, the proposed sandwiched-gate structure is also applied to fundamental logic circuits such as the NAND, NOR, and SRAM cell designs, and each operation is verified. The proposed logic gates achieve up to a 20% area reduction compared with the conventional GAA.
#Sandwiched gate #gate all around (GAA) #inverter #junctionless #TCAD #integrated circuits
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목차

  1. Abstract
  2. I. INTRODUCTION
  3. II. OPERATION OF PROPOSED INVERTER
  4. III. LOGIC APPLICATIONS: EXTENSION TO NAND, NOR, AND SRAM
  5. IV. CONCLUSIONS
  6. REFERENCES

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