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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.20 No.4
- 발행연도
- 2020.8
- 수록면
- 311 - 319 (9page)
- DOI
- 10.5573/JSTS.2020.20.4.311
이용수
초록· 키워드
오류제보하기
This paper describes a minimum energy tracking (MET) loop to allow load system to consume the minimum energy with changing workload and temperature. The proposed loop can track the minimum energy point more accurately by adopting an accurate energy sensing and a hierarchical tracking methods, resulting in more energy saving than the conventional approach. The proposed MET hardware has been fabricated in a 130nm CMOS process. The experimental results indicated that the accuracy of the proposed loop was improved up to 95% and 99.4% for light and heavy workload conditions, respectively, resulting in energy saving up to 38.7% as compared to the conventional loop.
목차
Abstract
I. INTRODUCTION
II. ENERGY OF DIGITAL CMOS CIRCUITS
III. PROPOSED MINIMUM ENERGY TRACKING HARDWARE
IV. MEASUREMENT AND DISCUSSION
V. CONCLUSION
REFERENCES
참고문헌 (9)
참고문헌 신청
M. Potocny, et al., “Self Vth-compensating CMOS on-chip rectifier for inductively powered implantable medical devices,” IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 158-161, 2018.
K. Yang, et al., Hardware designs for security in ultra-low-power IoT systems: an overview and survey, IEEE Micro, Vol. 37, Issue 6, pp. 72-89, 2017.
E. D. Manolov, “Design of CMOS analog circuits in subthreshold region of operation,” IEEE Int. Scientific Conference Electronics, pp. 1-4, 2018.
Mohammad S. et al., “A low-power temperaturecompensated CMOS peaking current reference in subthreshold region,” in IEEE International Symposium on Circuits and Systems, pp. 1-4, 2017.
J.-H. Park, et al., “Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application,” IEEE Trans. on VLSI Systems, vol. 25, no. 2, pp. 779-782, Feb. 2017.
K. Yang, et al., Hardware designs for security in ultra-low-power IoT systems: an overview and survey, IEEE Micro, Vol. 37, Issue 6, pp. 72-89, 2017.
E. D. Manolov, “Design of CMOS analog circuits in subthreshold region of operation,” IEEE Int. Scientific Conference Electronics, pp. 1-4, 2018.
Mohammad S. et al., “A low-power temperaturecompensated CMOS peaking current reference in subthreshold region,” in IEEE International Symposium on Circuits and Systems, pp. 1-4, 2017.
J.-H. Park, et al., “Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application,” IEEE Trans. on VLSI Systems, vol. 25, no. 2, pp. 779-782, Feb. 2017.
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