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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2020.8
- 수록면
- 646 - 649 (4page)
이용수
초록· 키워드
오류제보하기
In this paper, a 5.8-㎓ CMOS Fractional-N Frequency Synthesizer using Quadrature Voltage Controlled Oscillator(QVCO) is presented. A QVCO was used to Supply quadrature signals to TX and RX. To synthesize the DSRC target frequency, a Fractional-N Phase Locked loop(PLL) structure is used, and each sub-block has a low noise feature to reduce phase noise and reference spur which are important characteristics of the PLL. It is implemented in 0.13 um CMOS and the power consumption is 36 ㎽ from the supply voltage of 1.2 V. The measured phase noise of the VCO is respectively -108.66 ㏈c/㎐ at a 1-㎒ offset from carrier frequency of 5.8 ㎓. The measured tuning range of the VCO is about 20 %.
목차
Abstract
1. Introduction
2. Structure
3. Measurement Result
4. Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2020-569-001130434