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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국정보통신학회JICCE Journal of information and communication convergence engineering Journal of information and communication convergence engineering Vol.13 No.4
- 발행연도
- 2015.12
- 수록면
- 235 - 240 (6page)
이용수
초록· 키워드
오류제보하기
A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analogto-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.
목차
Abstract
I. INTRODUCTION
II. ALTERNATIVE CONFIGURATIONS FOR THE DECIMATION CHAIN
III. POLYNOMIAL INTERPOLATOR AND INTERPOLATION ERROR
IV. SELF-TIMING ADJUSTMENT FOR CPC
V. CONCLUSION
REFERENCES
참고문헌 (11)
참고문헌 신청
[학술지(정기간행물)] - B. A. White / 2000 / Low-power design of decimation filters for a digital IF receiver / IEEE Transactions on Very Large Scale Integration(VLSI)Systems 8 (3) : 339 ~ 345
[학술지(정기간행물)] - H. M. Chang / 2011 / Low-latency digital-IF scheme using an IIR polyphase filter structure for delay-sensitive repeater systems / IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences 94 (8) : 1715 ~ 1723
[학술지(정기간행물)] - M. Kim / 2009 / Efficient heterodyne digital receiver with direct RF-to-digital conversion for software defined radio / IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences 92 (4) : 1056 ~ 1062
[학술지(정기간행물)] - G. Hueber / 2008 / An adaptive digital front-end for multimode wireless receivers / IEEE Transactions on Circuits and Systems II : Express Briefs 55 (4) : 349 ~ 353
[학술대회논문] - R. Uusikartano / 2004 / A low-power fractional decimator architecture for an IF-sampling dual-mode receiver / Proceedings of the International Symposium on Circuits and Systems (ISCAS’04) : 589 ~ 592
[학술지(정기간행물)] - H. M. Chang / 2011 / Low-latency digital-IF scheme using an IIR polyphase filter structure for delay-sensitive repeater systems / IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences 94 (8) : 1715 ~ 1723
[학술지(정기간행물)] - M. Kim / 2009 / Efficient heterodyne digital receiver with direct RF-to-digital conversion for software defined radio / IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences 92 (4) : 1056 ~ 1062
[학술지(정기간행물)] - G. Hueber / 2008 / An adaptive digital front-end for multimode wireless receivers / IEEE Transactions on Circuits and Systems II : Express Briefs 55 (4) : 349 ~ 353
[학술대회논문] - R. Uusikartano / 2004 / A low-power fractional decimator architecture for an IF-sampling dual-mode receiver / Proceedings of the International Symposium on Circuits and Systems (ISCAS’04) : 589 ~ 592
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