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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전자파학회JEES Journal of Electromagnetic Engineering And Science Journal of Electromagnetic Engineering And Science Vol.24 No.1
- 발행연도
- 2024.1
- 수록면
- 98 - 107 (10page)
이용수
초록· 키워드
This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 V<SUB>pp</SUB> operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator’s input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator’s input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm² and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz.
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목차
- Abstract
- Ⅰ. INTRODUCTION
- Ⅱ. ARCHITECTURE
- Ⅲ. CIRCUIT DESCRIPTION
- Ⅳ. ERROR SOURCE CONSIDERATION
- Ⅴ. MEASUREMENT RESULTS
- Ⅵ. CONCLUSION
- REFERENCES
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