지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.24 No.3
- 발행연도
- 2024.6
- 수록면
- 184 - 190 (7page)
- DOI
- 10.5573/JSTS.2024.24.3.184
이용수
초록· 키워드
오류제보하기
A Delay compensation technique for implementing scalable high-speed logics has been proposed and its theoretical background has been analyzed fundamentally. Based on the scalable design methodology, the whole logics of proposed 2-channel transceiver operate successfully over the range of 2.65-6.4 Gb/s. The prototype chip has been fabricated in 65 nm CMOS process and occupies 1.02 ㎟ die area. The transceiver consumes 72 mW/lane from 1.2 V supply. The measured eye-openings show 28.7% improvement vertically in Tx output by pre-emphasis at 6.4 Gb/s. The built-in Rx BER counter shows 0.25 unit interval (UI) horizontal eye-opening improvement at 10<SUP>-9</SUP> BER in this speed.
목차
Abstract
I. INTRODUCTION
II. ARCHITECTURE
III. MEASUREMENT
IV. CONCLUSIONS
REFERENCES
참고문헌 (4)
참고문헌 신청
Frans, Y., Carey, D., Erett, M. et al: ‘A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS’ , IEEE Jornal of Solid-State Circuits, 2015, 50, 8, pp. 1932-1944, doi:10.1109/JSSC.2015.2413849.
Abdollahi, R., Hadidi, K. and Khoei, A.: ‘A Simple and Reliable System to Detect and Correct Setup/Hold Time Violations in Digital Circuits’,IEEE Transactions on Circuits and Systems I: Regular Paper 2016, 63, 10, pp. 1682-1689, doi:10.1109/TCSI.2016.2582239.
Savoj, J., Hsieh, K.C.H., An, F.T. et al: ‘A Low-Power 0.5-6.6Gb/s Wireline Transceiver Embedded in Low-Cost 28nm FPGAs’, IEEE Journal of Solid-State Circuits, 2013, 48, 11, pp. 2582-2594, doi:10.1109/JSSC.2013.2274824.
Faust, A.C., Narasimha, R.L., Bhatia, K. et al: ‘FEC-based 4 Gb/s backplane transceiver in 90nm CMOS’, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, USA, 9-12 Sept. 2012, doi:10.1109/CICC.2012.6330665.
Abdollahi, R., Hadidi, K. and Khoei, A.: ‘A Simple and Reliable System to Detect and Correct Setup/Hold Time Violations in Digital Circuits’,IEEE Transactions on Circuits and Systems I: Regular Paper 2016, 63, 10, pp. 1682-1689, doi:10.1109/TCSI.2016.2582239.
Savoj, J., Hsieh, K.C.H., An, F.T. et al: ‘A Low-Power 0.5-6.6Gb/s Wireline Transceiver Embedded in Low-Cost 28nm FPGAs’, IEEE Journal of Solid-State Circuits, 2013, 48, 11, pp. 2582-2594, doi:10.1109/JSSC.2013.2274824.
Faust, A.C., Narasimha, R.L., Bhatia, K. et al: ‘FEC-based 4 Gb/s backplane transceiver in 90nm CMOS’, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, San Jose, CA, USA, 9-12 Sept. 2012, doi:10.1109/CICC.2012.6330665.
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