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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.25 No.3
- 발행연도
- 2025.6
- 수록면
- 274 - 283 (10page)
- DOI
- 10.5573/JSTS.2025.25.3.274
이용수
초록· 키워드
In this study, we present a design technique that minimizes drain current fluctuations due to temperature changes and utilizes the concept of zero-temperature coefficient (ZTC) points to increase the stability of the one-transistor (1T) DRAM operation. In particular, the reliability of temperature changes was secured by maintaining the stability of drain current in a high-temperature (300 K-400 K) environment through optimization of ZTC operation voltage, and data retention time and stability were strengthened by applying an asymmetric dual-gate structure. In addition, by optimizing the size of the device and adjusting the main gate work function (WF1) and body doping concentration, stable data retention performance was confirmed even in a high-temperature environment. These designs minimize leakage current and maintain data retention times up to 330 ms to ensure reliable memory operation under various environmental conditions.
#One-transistor dynamic random access memory
#zero-temperature coefficient point
#device parameter
#sensing margin
#retention time
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목차
- I. INTRODUCTION
- II. DEVICE STRUCTURE
- III. RESULTS AND DISCUSSION
- IV. CONCLUSIONS
- REFERENCES
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