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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.25 No.5
- 발행연도
- 2025.10
- 수록면
- 502 - 508 (7page)
- DOI
- 10.5573/JSTS.2025.25.5.502
이용수
초록· 키워드
We propose a highly scalable ternary CMOS (T-CMOS) technology using halo implantation in commercial 28-nm process. By forming a locally confined halo profile, VDS-dependent constant band-to-band tunneling (BTBT) current is successfully obtained which enables VDD-scalable subthreshold ternary operation. The merged halo profile near source/drain junction exhibits excellent short-channel behavior and facilitates the suppression of the tunneling current with a reduced ion dose than retrograde one, while maintaining the same VT design. Halo energy and tilt angle are introduced as additional design knobs to further reduce the tunneling current, expanding the T-CMOS design window. Therefore, low-power ternary operation is demonstrated in a wide-bias range from 1.0 V to 0.3 V, with sub-picoampere level leakage. By leveraging an additional VDD/2 latch state that enables 1.5-bits per cell storage in a high-density 6T bitcell, our T-SRAM achieves 0.62 pW/bit leakage power and nearly a 10× improvement in the figure-of-merit (cell density / leakage power) over prior reported low-leakage SRAMs.
#Halo profile
#band-to-band tunneling
#T-CMOS
#enhanced design window
#low-leakage and high-density T-SRAM
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목차
- Abstract
- I. INTRODUCTION
- II. T-CMOS BY EXPLOITING HALO PROFILE
- III. SCALABILITY OF HALO T-CMOS
- IV. LOW-LEAKAGE AND HIGH-DENSITY TERNARY-SRAM
- V. CONCLUSIONS
- REFERENCES
참고문헌
참고문헌 신청최근 본 자료
UCI(KEPA) : I410-151-26-02-094303183
