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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.25 No.6
- 발행연도
- 2025.12
- 수록면
- 679 - 687 (9page)
- DOI
- 10.5573/JSTS.2025.25.6.679
이용수
초록· 키워드
This paper presents a low-power time-to-digital converter (TDC) designed for duty-cycle correction in NAND Flash memory interfaces. The proposed 5.5-bit two-step Vernier TDC integrates coarse and fine delay stages to support a wide timing range with compact implementation. A charge elimination circuit is incorporated into the true single-phase clocked (TSPC) sampling register to mitigate hold-time metastability with minimal area overhead. In addition, a twist power-gating (TPG) technique is applied to the delay chains to reduce leakage current with minimal impact on delay and performance. These techniques are suitable for multi-die memory systems requiring low standby current and compact layout. The TDC is fabricated in a 28-nm FD-SOI process using 150-nm thickoxide transistors to emulate NAND Flash interface conditions. Measurement results demonstrate a resolution of 3.64 ps at 100 MS/s and a power consumption of 0.9 mW. The core occupies an area of 0.0025 mm². The design achieves a balanced trade-off among resolution, power, and area, confirming its applicability to high-speed, lowpower memory interfaces.
#Time-to-digital converter (TDC)
#Vernier TDC
#metastability mitigation
#twist power-gating
#NAND Flash memory interface
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목차
- Abstract
- Ⅰ. INTRODUCTION
- Ⅱ. PROPOSED TDC ARCHITECTURE
- Ⅲ. CIRCUIT DETAILS
- Ⅳ. SIMULATION AND MEASUREMENT RESULTS
- Ⅴ. CONCLUSIONS
- REFERENCES
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