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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2011.6
- 수록면
- 41 - 50 (10page)
- DOI
- http://dx.doi.org/10.14257/AJMAHS.2011.06.03
이용수
초록· 키워드
Voice-over Internet Protocol (VoIP) telephony which is the transmission of real-time voice over an internet protocol (IP) data network, is increasingly becoming a variant telecommunication technology that one day may surpass the old analog and digital telephone systems. The Quality-of-Service (QoS) factor is an important parameter to be considered when measuring the performance of a VoIP system. Algorithmic delay (latency) may influence the QoS of a VoIP system.
This paper presents the hardware implementation of the Open-Loop Pitch Analysis component of the Conjugate-Structure Algebraic-Code-Excited Linear-Prediction (CS-ACELP) speech compression algorithms. The Open-Loop Pitch Analysis units were implemented in hardware using Xilinx 11.1 ISE, after which ITU-T test vectors were used to determine whether they were equivalent implementations of the Open-Loop Pitch Analysis. The algorithmic delays of hardware-implementations were obtained via simulation using Modelsim XE 6.4b while the algorithmic delays of the software-implemented speech compression algorithms were obtained by software profiling using the GPROF profiler.
After comparison the algorithmic delays of the hardware-implementations of the Open-Loop Pitch Analysis was found to be shorter than the algorithmic delays of their software-implemented and hardware-implemented counterparts.
#Open-loop
#Open-loop
#Open-Loop Pitch Analysis
#Open-Loop Pitch Analysis
#Pitch Analysis
#Pitch Analysis
#Hardware Implementation
#Hardware Implementation
#Speech Compression Algorithm
#Speech Compression Algorithm
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