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논문 기본 정보

자료유형
학위논문
저자정보

강태수 (충북대학교, 충북대학교 대학원)

지도교수
김영철
발행연도
2015
저작권
충북대학교 논문은 저작권에 의해 보호받습니다.

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이 논문의 연구 히스토리 (2)

초록· 키워드

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This thesis presents a technique modeling a vector controlled permanent magnet synchronous motor(PMSM) drive system and design of the direct digital speed controller based on the multiple model adaptive control(MMAC) method. Especially, we consider the PMSM drive system of which load and disturbance may vary, as seen in the electric vehicle equipped with a PMSM drive. Number of passengers is equal to the payload and the road grade is modeled by a disturbance. Moreover, the motor drive for electric vehicle is required to well follow the variable reference speed which is given by a driver. If the conventional fixed-gain controller based on the equivalent circuit model of the PMSM is used for this system, its performance may be poor because the variation of load makes the dynamics change. The vector control system of the PMSM drive can be implemented by two control loops: current control loop and velocity control loop. We begin with modeling of the equivalent plant in
* A thesis for the degree of Master in February 2015.
the current loop by means of the closed-loop identification(CLID) algorithm. To perform this, any stable controller, for example either proportional or PI controller is first chosen. A pseudorandom binary sequence(PRBS) type test input of 10% is added on the reference current input and then acquire the current output simultaneously. By applying the recursive CLID algorithm to these data, the parameters of a discrete-time plant model are identified. In order to apply the MMAC to the current controller, we need to select N operating points in the manner of dividing the possible maximum current range into N parts. In our experiments, four current points have been selected as the operating points. In the MMAC scheme, a linear time-invariant model corresponding to each operating point must be known in advance. Thus, four models for the equivalent plant in the current loop have been identified by repeating the identification procedure at every operating point. Each model () has its own digital controller () which is designed using the discrete-time characteristic ratio assignment (DCRA) developed by Kim. It is general that the settling time of the current loop should be much faster than that of velocity loop. The adaptation rule is to calculate the weighting factors which are dependent on operating points and the present current. Then the control output is determined by a linear combination of every control () multiplied by their weighting factor.
Once the current controller is designed, the equivalent plant model including the current controller in the speed control loop is identified by using the same CLID algorithm as the previous one. Based on the discrete-time plant model, the digital velocity controller is designed using the DCRA again. We conclude through experiments that it is not necessary to apply the MMAC to the speed controller because velocity models are not varied so much even though its load changes over wide range.
The proposed method was demonstrated through simulations and experiments. The experimental set up consists of SPMSM (5 Kw, 3, 220V) equipped with a flywheel load of 220Kg, an intelligent power module (PS21A7A, 600V, 75A, Mitsubishi) as a PWM inverter, and a micro controller (TMS320F28335, 32bit, 150Mhz/150MMAC, TI).
As a result, it is shown that all the performances coincide closely with those of simulations over the full range of current. The ISE performance is improved 30% more than that of a fixed-gain current controller.

목차

Ⅰ. 서론 1
1.1 연구배경 및 필요성 1
1.2 연구목적 3
1.3 연구내용 3
Ⅱ. 영구자석 동기전동기 및 벡터제어 5
2.1 영구자석 동기전동기 6
2.2 좌표변환 7
2.3 벡터제어 10
2.4 다중모델 적응제어기법의 필요성과 고려하는 문제점 12
Ⅲ. 다중모델 적응제어기법을 이용한 동기전동기의 속도제어기 설계 14
3.1 다중모델 적응제어기법의 개요 15
3.2 동기전동기 폐루프 모델링 및 디지털제어기 직접 설계 18
3.2.1 동기전동기 전류 제어 루프의 폐루프 모델링 19
3.2.2 동기전동기 전류 제어 루프의 디지털제어기 직접 설계 20
3.2.3 동기전동기 속도 제어 루프의 폐루프 모델링 22
3.2.4 동기전동기 속도 제어 루프의 디지털제어기 직접 설계 24
3.3 동기전동기 속도제어 시스템의 다중모델 적응제어 26
Ⅳ. 시뮬레이션 및 실험결과 28
4.1 시스템의 하드웨어 구성 29
4.2 시뮬레이션 및 실험결과 35
Ⅴ. 결론 44
참고문헌 47
부록 49
부록A 49
부록B 54

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