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논문 기본 정보

자료유형
학위논문
저자정보

오찬수 (성균관대학교, 성균관대학교 일반대학원)

지도교수
엄영익
발행연도
2016
저작권
성균관대학교 논문은 저작권에 의해 보호받습니다.

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이 논문의 연구 히스토리 (2)

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In general, current mobile devices employ a buffer cache mechanism which has been designed to mitigate the performance gap between CPU and storage. However, it cannot fit in mobile devices because it does not consider the characteristics of the mobile applications (e.g., foreground or background state). Therefore, existing buffer cache mechanisms can cause performance degradation by I/O interference between foreground applications and background applications. In addition, DRAM accelerates energy consumption by performing periodic refresh operations. Therefore, DRAM-based memory system can cause critical power problem due to its limited battery capacity in the mobile devices. In this paper, we propose a novel buffer cache algorithm for mobile devices based on hybrid memory architecture composed of DRAM and non-volatile PCM. Proposed algorithm is based on key observation that background applications rarely issue I/O requests and foreground applications generate most of I/O requests. For evaluation, we implemented the proposed algorithm and compared the performance with two widely known algorithms. Our experimental results show that our algorithm reduces the elapsed time of the foreground applications by 70% on average and the power consumption by 67% on average while operating same workloads.

목차

Abstract 1
1. Introduction 3
2. Related works 5
3. Proposed algorithm 9
3.1 Critical process 11
3.2 Non-critical process 13
4. Experiment and evaluation 15
4.1 Experimental preparation 15
4.2 Evaluation 17
4.2.1 Critical process intensive workload 18
4.2.2 Non-critical process intensive workload 20
4.2.2 Balanced state workload 22
4.2.2 Stand-by state workload 24
4.3 Energy consumption 26
5. Conclusion 28
References 29
Korean Abstract 32

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