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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국과학기술원 정보전자연구소 IDEC Journal of Integrated Circuits and Systems IDEC Journal of Integrated Circuits and Systems Vol.3 No.1
- 발행연도
- 2017.1
- 수록면
- 1 - 6 (6page)
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초록· 키워드
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A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with an averaging circuit (AC) and an effectively negative feedback functioned capacitor is presented. The AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal 0.18μm CMOS process shows 13.4-ps rms jitter.
목차
등록된 정보가 없습니다.
참고문헌 (12)
참고문헌 신청
Sander L. J. Gierkink / 2008 / Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and self-correcting charge pump / IEEE J. Solid-State Circuits 43(12):2967~2976
Q. Du, J. Zhuang / 2006 / A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction / IEEE Trans. Circuits Syst. II 53(11):1205~1209
G. Chien / 2000 / A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications / IEEE J. Solid-State Circuits 35(12):1996~1999
D. J. Foley / 2001 / CMOS DLL-based 2-V 3. 2-ps jitter 1-GHz clock synthesizer and temperaturecompensated tunable oscillator / IEEE J. Solid-State Circuits 36(3):417~423
J. Koo / 2009 / A low-power programmable DLL-based clock generator with wide-range anti harmonic lock / IEEE Trans. Circuits Syst. II 56(1):21~25
Q. Du, J. Zhuang / 2006 / A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction / IEEE Trans. Circuits Syst. II 53(11):1205~1209
G. Chien / 2000 / A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications / IEEE J. Solid-State Circuits 35(12):1996~1999
D. J. Foley / 2001 / CMOS DLL-based 2-V 3. 2-ps jitter 1-GHz clock synthesizer and temperaturecompensated tunable oscillator / IEEE J. Solid-State Circuits 36(3):417~423
J. Koo / 2009 / A low-power programmable DLL-based clock generator with wide-range anti harmonic lock / IEEE Trans. Circuits Syst. II 56(1):21~25
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