지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2024.11
- 수록면
- 333 - 336 (4page)
이용수
초록· 키워드
오류제보하기
Since delay-locked loops (DLLs) are widely used for phase deskew or multi-phase generation in many high-speed interfaces, the jitter performance of the output clock is very important. Supply voltage noise of the voltage-controlled delay line in a DLL causes poor output jitter performance. In this paper, a supply noise insensitive DLL with a source follower-based low dropout regulator is proposed and designed in a 28nm process. The proposed DLL exhibits an output clock jitter of 1.19ps at 30mVpp supply noise at 10MHz frequency, which is reduced by 42% compared to the conventional DLL. Power supply rejection is also greatly improved over the entire frequency range. In addition, the jitter performance further improves as the frequency increases.
목차
Abstract
I. Introduction
II. Proposed DLL Design
Ⅲ. Simulation Results
Ⅳ. Conclusion
References
참고문헌 (0)
참고문헌 신청함께 읽어보면 좋을 논문
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
-
A Wide-Range Duty-Independent All-Digital Quadrature-Phase Clock Generator
IDEC Journal of Integrated Circuits and Systems
2017 .10
-
A Digital DLL with 4-Cycle Lock Time and 1/4 NAND-Delay Accuracy
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .08
-
New charge pump with perfect current matching characteristics for low-jitter PLL applications
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2015 .06
-
A 300MHz-800MHz Low Jitter Injection Locked Frequency Multiplier for Low Power applications
대한전자공학회 학술대회
2019 .11
-
Harmonic Lock을 예방하고 PVT Variation에 둔감한 Multiplying Delay Locked Loop 설계
대한전자공학회 학술대회
2021 .06
-
An All-digital Delay-locked Loop using a Lock-in Pre-search Algorithm for High-speed DRAMs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .12
-
A Capacitor-less Low Dropout Regulator for Enhanced Power Supply Rejection
IEIE Transactions on Smart Processing & Computing
2015 .06
-
지연 고정 루프 회로의 지터 분석 및 저감 방법 연구
대한전자공학회 학술대회
2022 .11
-
A 10.2-GHz LC-VCO for a 28-nm CMOS Transmitter With Nearest VCO-curve Selection Algorithm
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2020 .06
-
Design of a Transceiver Transmitting Power, Clock, and Data over a Single Optical Fiber for Future Automotive Network System
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2017 .02
-
Analysis on Power Noise Induced Jitter Characteristics in Pseudo Differential Signaling
대한전자공학회 학술대회
2019 .06
-
A Random and Systematic Jitter Suppressed DLL-Based Clock Generator with Effective Negative Feedback Loop
IDEC Journal of Integrated Circuits and Systems
2017 .01
-
250 mV Supply Voltage Digital Low-Dropout Regulator Using Fast Current Tracking Scheme
[ETRI] ETRI Journal
2015 .10
-
A DLL-based reference-less CDR with ISI jitter reduction scheme for clock-embedded signaling in 65nm process
IDEC Journal of Integrated Circuits and Systems
2017 .10
-
자동 고속 Settling method의 저역 통과 필터를 사용한 저잡음 Low Dropout Voltage Regulator 설계
대한전자공학회 학술대회
2021 .06
-
An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2016 .02
-
안티-바운드리 스위칭 디지털 지연고정루프
전기전자학회논문지
2017 .12
-
디지털 로직을 통해 빠른 주파수 고정이 가능한 875MHZ Sub-Sampling 위상 고정 루프
대한전자공학회 학술대회
2019 .11
-
PVT Variation 보상을 위한 Dynamically Phase Error 추적 기능을 갖춘 저전력 All Digital Delay Locked Loop
한국전자파학회논문지
2020 .07
-
Analysis and Optimization of Phase Noise of 2 ㎓ All-Digital Phase-Locked Loop
대한전자공학회 학술대회
2020 .08
이 논문과 함께 이용한 논문
최근 본 자료
댓글(0)
0