Test Generation for Sequential Circuits

Dong Ho Lee

대한전자공학회 학술대회

1994 .07

Test Generation for Sequential Circuits Using Partitioned Image Computation

Ho Yong Choi ,  Hi ,  ono 외 10명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1993 .01

Feedback Analysis of Sequential Circuits

Edwa ,  d Chin Hsi Ling ,  Tay Beng Kang

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1994 .01

Generation of All prime Implicates by Using BDD ( Binary Decision Diagram )

Kimio Goto ,  Takashi Ito ,  Xiaoping Lin

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1994 .01

Optimal Allocation of VLSI Data Path Using Binary Decision Diagram

Satoshi Yamanaka ,  Shoichi ,  o Yamada

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1997 .01

A Study on the Circuit Minimization Technique Using Edge Multiple-Valued Decision Diagrams

Sung Il Han ,  Jong Hak Hwang ,  Boo Sik Shin 외 3명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1997 .01

河川流量의 Sequential Generation에 관한 硏究

李舜鐸

대한토목학회지

1971 .12

An Automatic Test Pattern Generator for Sequential Circuits with Three-State Elements

Beom Ik Cheon ,  Walte ,  Anheie 외 2명

ICVC : International Conference on VLSI and CAD

1997 .01

시이컨셜회로 구현에 관한 연구

박춘명

대한전자공학회 학술대회

2012 .11

A Parallel Algorithm For The Synthesis of Sequential Circuits

Lu Ying Ping ,  Wang Wen Zhang

대한전자공학회 기타 간행물

1992 .01

An Improvement of a State Encoding Algorithm for Sequential Circuits

Nobuhiko Ito ,  Agus Ha ,  nowo 외 1명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1991 .01

이진결정 그래프를 이용한 비동기 회로의 초기화 ( An Initialization Issue of Asynchronous Circuits Using Binary Decision Diagram )

김수현 ,  이정근 ,  최호용 외 1명

대한전자공학회 학술대회

1998 .07

이진결정 그래프를 이용한 비동기 회로의 초기화

김수현 ,  이정근 ,  최호용 외 1명

대한전자공학회 학술대회

1998 .06

다이어그램을 통한 건축형태생성 프로세스 연구

한상길 ,  이공희

대한건축학회 학술발표대회 논문집 - 계획계

2005 .10

Design and Simulation of Neural Network Digital Sequential Circuits

Hi ,  oshi Ninomiya ,  Hideki Asai

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1993 .01

TEST GENERATION FOR SEQUENTIAL CIRCUIT BASED ON BOOLEAN FUNCTION MANIPULATION

Ho Yong Choi ,  Takashi Koba ,  a 외 7명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1992 .01

다이어그램을 통한 현대건축의 형태생성 프로세스 연구

한상길 ,  이공희

대한건축학회 논문집 - 계획계

2006 .09

회로 분할에 의한 순차회로의 테스트생성 ( Test Generation for Sequential Circuits Based on Circuit Partitioning )

최호용

전자공학회논문지-C

1998 .04

SCHEMATIC DIAGRAM GENERATION

Seok Jin Seo ,  Jong Wha Chong

ICVC : International Conference on VLSI and CAD

1989 .01